ARM: Introduce ability to enable invalidate of BTB with ICIALLU on Cortex-A15 for...

As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB)
needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to
be done unconditionally for Cortex-A15 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.

NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
   provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the
   right locations.
c) This workaround applies to only the boot processor. It is important
   to apply workaround as necessary (context-save-restore) around low
   power context loss OR additional processors as necessary in either
   firmware support OR elsewhere in OS.

[1] https://developer.arm.com/support/security-update
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html

Cc: Marc Zyngier <[email protected]>
Cc: Russell King <[email protected]>
Cc: Tony Lindgren <[email protected]>
Cc: Robin Murphy <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Christoffer Dall <[email protected]>
Cc: Andre Przywara <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Michael Nazzareno Trimarchi <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Tested-by: Fabio Estevam <[email protected]>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ba8b0ccbd262baa060e000bedf108f4c9561b617..00b28480b4091ad2679dc6948311d81ca8488b6d 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -109,6 +109,7 @@ config SYS_ARM_MPU
 # CONFIG_ARM_ERRATA_798870
 # CONFIG_ARM_ERRATA_801819
 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
+# CONFIG_ARM_CORTEX_A15_CVE_2017_5715
 
 config ARM_ERRATA_430973
        bool
@@ -182,6 +183,9 @@ config ARM_ERRATA_855873
 config ARM_CORTEX_A8_CVE_2017_5715
        bool
 
+config ARM_CORTEX_A15_CVE_2017_5715
+       bool
+
 config CPU_ARM720T
        bool
        select SYS_CACHE_SHIFT_5

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 3beaf5a93d815ce2bffc3ac655f79a4f47b68db4..81edec01bf32d3bf8b8698a535a27727a9875e99 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -241,6 +241,14 @@ skip_errata_798870:
 skip_errata_801819:
 #endif
 
+#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
+       mrc     p15, 0, r0, c1, c0, 1   @ read auxilary control register
+       orr     r0, r0, #1 << 0         @ Enable invalidates of BTB
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_454179
        mrc     p15, 0, r0, c1, c0, 1   @ Read ACR